13.8 Interrupt Sequence

All interrupt event flags are sampled in the system clock by the IFSx registers. A pending Interrupt Request (IRQ) is indicated by the flag bit being equal to a ‘1’ in an IFSx register. The IRQ will cause the interrupt to occur if the corresponding bit in the Interrupt Enable (IECx) register is set. For the next clock cycle, the priorities of all pending interrupt requests are evaluated.

If there is a pending IRQ with a priority level greater than the current processor priority level in the processor Status register, an interrupt will be presented to the processor. No instruction is aborted when the CPU responds to the IRQ. When the IRQ is sampled, the instruction in progress is completed before the Interrupt Service Routine (ISR) is executed.

The interrupt request, its associated vector number, and the new Interrupt Priority Level (IPL) are latched into ILR, VECNUM, and IRQCPU bit fields in the INTTREG register to keep them stable through the interrupt process. The processor reacts to the interrupt request by asserting the IACK (interrupt Acknowledge) signal to prevent the ILR, VECNUM and IRQCPU bits from changing during the interrupt process.

The processor then stacks the current Program Counter and the low byte of the processor status register. The low byte of the status register contains the processor priority level at the time prior to the beginning of the interrupt cycle.

The processor then takes the priority level for this interrupt and loads it into the processor status register. This action will disable all lower priority interrupts until the completion of the ISR. Additionally, the CTX bits of the SR register are automatically updated to the value of the IPL, thereby triggering a hardware context switch prior to entering the ISR.

After servicing the interrupt, the RETFIE (Return from Interrupt) instruction will unstack the Program Counter and status registers to return the processor to its state prior to the interrupt sequence.

The processor IPL register is a 4-bit register. The IPL bits are available in the Processor Status Register (SR).

The MSB of the SR.IPL register is set if a trap is being processed. There are seven levels of user IPLs, and eight priority levels for traps (two levels are reserved plus six traps).