18.1 Device-Specific Information

Table 18-1. ADC Summary
Number of CoresNumber of ChannelsMax Input ClockClock SourcePeripheral Bus Speed
220320 MHzCLKGEN6Fast

The number of available positive and negative analog inputs is dependent on package size, as shown in the table below.

Table 18-2. ADC External Input Availability
ADC Input28-Pin36-Pin48-Pin64-PinComments
AD1ANN0AVSSADC 1 ground negative input 0 supporting Differential mode
AD1ANN1XXXX

ADC 1 negative input 1 supporting Differential mode

AD1ANN2XX

ADC 1 negative input 2 supporting Differential mode

AD1ANN3XX

ADC 1 negative input 3 supporting Differential mode

AD1AN0XXXXADC 1 positive input 0
AD1AN1XXXXADC 1 positive input 1
AD1AN2XXXADC 1 positive input 2
AD1AN3XXXADC 1 positive input 3
AD1AN4XXXXADC 1 positive input 4
AD1AN5XXXXADC 1 positive input 5
AD1AN6XXADC 1 positive input 6
AD1AN7XXXXADC 1 positive input 7
AD1AN8XXADC 1 positive input 8
AD1AN9XXADC 1 positive input 9
AD1AN10XADC 1 positive input 10
AD1AN11XADC 1 positive input 11
AD1AN13InternalADC 1 die temperature diode
AD1AN14Internal ADC 1 15/16*VDD reference input
AD1AN15InternalADC 1 Band Gap 0.8V reference input
AD2ANN0AVSSADC 2 ground negative input 0 supporting Differential mode
AD2ANN1XXXX

ADC 2 negative input 1 supporting Differential mode

AD2ANN2XX

ADC 2 negative input 2 supporting Differential mode

AD2ANN3X

ADC 2 negative input 3 supporting Differential mode

AD2AN0XXXXADC 2 positive input 0
AD2AN1 XXXXADC 2 positive input 1
AD2AN2XXXADC 2 positive input 2
AD2AN3 XXXXADC 2 positive input 3
AD2AN4 XXXXADC 2 positive input 4
AD2AN5 XXXXADC 2 positive input 5
AD2AN6XXXXADC 2 positive input 6
AD2AN7 XADC 2 positive input 7
AD2AN8 XXADC 2 positive input 8
AD2AN9 XXADC 2 positive input 9
AD2AN10 XADC 2 positive input 10
AD2AN11InternalADC 2 VDDCORE input
AD2AN12 InternalADC 2 VREG input
AD2AN13InternalADC 2 PLL VREG input
AD2AN14InternalADC 2 15/16*VDD reference input
AD2AN15InternalADC 2 Band Gap 0.8V reference input
Table 18-3. TRG1SRC Trigger Source Selection Bits
ValueDescription
11111ADTRG31 (PPS)
11110PTG Trigger 12
11101CLC2 out
11100CLC1 out
11011-11000Reserved
10111SCCP4 OCMP/ICAP out
10110SCCP3 OCMP/ICAP out
10101SCCP2 OCMP/ICAP out
10100SCCP1 OCMP/ICAP out
10011Reserved
10010CLC4 out
10001CLC3 out
10000Reserved
01111SCCP4 Trigger out
01110SCCP3 Trigger out
01101SCCP2 Trigger out
01100SCCP1 Trigger out
01011PWM4 ADC Trigger 2
01010PWM4 ADC Trigger 1
01001PWM3 ADC Trigger 2
01000 PWM3 ADC Trigger 1
00111 PWM2 ADC Trigger 2
00110 PWM2 ADC Trigger 1
00101 PWM1 ADC Trigger 2
00100 PWM1 ADC Trigger 1
00011-00010Reserved
00001 Software trigger initiated using ADnSWTRG register
00000Triggers are disabled
Table 18-4. TRG2SRC Trigger Source Selection Bits
ValueDescription
11111ADTRG31 (PPS) falling edge
11110PTG Trigger 12
11101CLC2 out
11100CLC1 out
11011-11000Reserved
10111SCCP4 OCMP/ICAP out
10110SCCP3 OCMP/ICAP out
10101SCCP2 OCMP/ICAP out
10100SCCP1 OCMP/ICAP out
10011Reserved
10010CLC4 out
10001CLC3 out
10000Reserved
01111SCCP4 Trigger out
01110SCCP3 Trigger out
01101SCCP2 Trigger out
01100SCCP1 Trigger out
01011PWM4 ADC Trigger 2
01010PWM4 ADC Trigger 1
01001PWM3 ADC Trigger 2
01000 PWM3 ADC Trigger 1
00111 PWM2 ADC Trigger 2
00110 PWM2 ADC Trigger 1
00101 PWM1 ADC Trigger 2
00100 PWM1 ADC Trigger 1
00011Conversion repeat timer trigger defined by RPTCNT[5:0] (ADnCON[23:18]) bits
00010 Immediate re-trigger request
00001 Software trigger initiated using ADnSWTRG register
00000Triggers are disabled