16.6 DMA Interrupts

Each DMA channel has its own set of four interrupt flags, used to indicate a range of conditions during and following data transfers. Setting any of these flags with an interrupt event causes the device-level DMA Channel x Interrupt Flag (DMAxIF) to be set. With one exception, these flags are always enabled and not configurable. The DMAxIE bits, located in the IECx interrupt registers, will determine if a device-level interrupt is actually generated.

Since any of the DMA channel’s individual event flags can trigger a device-level interrupt for the channel, the user must include a method within the ISR to determine which flag triggered the interrupt.

The four DMA channel interrupts are:
  • DMA completion interrupt
  • DMA halfway point interrupt
  • Overrun interrupt
  • Pattern match interrupt
Apart from these, the DMA trap is generated when there are bus error conditions, such as:
  • Address Fault
  • Bus write error
  • Bus read error

In all of these conditions, the DMA will suspend its operation and the CHEN bit will be cleared.