1.4 Clocking Structure

The following figure shows the clocking structure of PCIe EndPoint reference design.

  • Clock Domain 1: Generates PCIe TL_CLK. At power-up, it uses 80 MHz clock and switches to 
125 MHz after completion of PCIe initialization.
  • Clock Domain 2: Generates CDR reference and XCVR clocks for PCIe.
  • Clock Domain 3: Generates 50 MHz clock for PCIe APB, DDR4 PLL reference and CCC reference clocks. DDR4 subsystem generates a 200 MHz (166.66 MHz for Splash kit) clock for fabric AXI interface logic. DDR3L subsystem generates 166.66 MHz clock and is connected to AXI interconnect target2 CDC interface.
Figure 1-10. Clocking Structure