1.7 Simulating the Design

Before you begin, perform the following steps:

  1. Start Libero SoC in the Project menu, and click Open Project.
  2. Browse mpf_an4597_df/HW/Eval_Kit or mpf_an4597_df/HW/Splash_Kit. For simulation, create the Libero Project using provided TCL scripts. To create the Libero Project, see Appendix 4 : Running the TCL script section.

The PCIe BFM performs 1 KB DMA operations between PCIe and DDR3L, DDR4 and LSRAM memories by initiating AXI burst transactions. The PCIe BFM simulation model replaces the entire PCIe EndPoint interface with a simple BFM that can send write transactions and read transactions over the AXI interface. These transactions are driven by a script file (.bfm) and allow easy simulation of the FPGA design connected to a PCIe interface. For more information about BFM commands, see PolarFire Family PCI Express User Guide . The micron DDR3L and DDR4 memory models are instantiated in the testbench for simulating DDR3L and DDR4 memory controllers.

Important: In the Design Flow tab, system verilog is selected, as the memory models from Micron are in the system verilog.
In the Project settings > Design Flow tab, double-click Simulate under Verify Pre-Synthesized Design to simulate the design. The ModelSim tool takes 10 to 15 minutes to complete the simulation, see the following figure.
Figure 1-12. Simulating the Design