1.3 Demo Design
(Ask a Question)Any external PCIe root-port or bridge can establish a PCIe link with the PolarFire FPGA PCIe EndPoint and access the control registers, DDR3L, DDR4 and fabric memory through BAR space using the Memory Write (MWr) and Memory Read (MRd) Transaction Layer Packets (TLPs). The PCIe EndPoint converts these MWr and MRd TLPs into AXI4 initiator interface transactions and accesses the fabric memory through CoreAXI4Interconnect IP.
The PCIe Demo application on the host PC initiates the DMA transfers through the PCIe Device drivers (Windows 10 and Linux Kernel version 6.8). The driver on the host PC allocates memory and initiates the DMA Engine in the PolarFire PCIe controller by accessing the PCIe DMA registers through BAR0. The PCIe controller has the following two independent DMA Engines:
- DMA Engine0: Performs DMA from host PC memory to DDR3L/DDR4/LSRAM
- DMA Engine1: Performs DMA from DDR3L/DDR4/LSRAM to host PC memoryImportant: For SGDMA type of DMA operations, the PCIe driver finds the available memory locations and creates the buffer descriptor chain for the different memory locations. It also configures the PCIe DMA for SGDMA and the base address of the first buffer descriptor.
The PCIe demo application initiates CoreAXI4DMA controller IP to perform the DMA between DDR3L memory and LSRAM. The following are the two channels of the CoreAXI4DMA controller IP:
- Channel0: Performs DMA from—DDR3L to DDR4, DDR3L to LSRAM and DDR4 to LSRAM
- Channel1: Performs DMA from—DDR4 to DDR3L, LSRAM to DDR3L and LSRAM to DDR4
The host PC application initiates the CoreAXI4DMA controller IP depending on the DMA type through BAR2 when the PCIe edge connector is connected to the host PC PCIe slot. The host PC application also initiates the CoreAXI4DMA controller IP through UART IF. This option is provided to exercise the DDR throughputs when the PolarFire Evaluation or Splash kit is not connected to the host PC PCIe slot.
