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PolarFire FPGA PCIe EndPoint DDR3L DDR4 Memory Controller Data Plane Application Note AN4597
PolarFire FPGA PCIe EndPoint DDR3L DDR4 Memory Controller Data Plane Application Note AN4597
  1. Home
  2. 1 PolarFire FPGA PCIe EndPoint, DDR3L, and DDR4 Memory Controller Data Plane
  3. 1.2 Prerequisites
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AN4597

  • Introduction
  • 1 PolarFire FPGA PCIe EndPoint, DDR3L, and DDR4 Memory Controller Data Plane
    • 1.1 Design Requirements
    • 1.2 Prerequisites
    • 1.3 Demo Design
    • 1.4 Clocking Structure
    • 1.5 Reset Structure
    • 1.6 Throughput Measurement
    • 1.7 Simulating the Design
  • 2 Run PROGRAM Action for Evaluation Kit
  • 3 Run PROGRAM Action for Splash Kit
  • 4 Running the Demo
  • 5 Appendix 1: DDR3L and DDR4 Power Measurement
  • 6 Appendix 2: DDR4 Configuration
  • 7 Appendix 3: DDR3L Configuration
  • 8 Appendix 4: Programming the Device Using FlashPro Express
  • 9 Appendix 5: Running the TCL Script
  • 10 Appendix 6: References
  • 11 Revision History
  • Microchip FPGA Support
  • Microchip Information

1.2 Prerequisites

(Ask a Question)
Before you begin, perform the following steps:
  • For demo design files, download the link from AN4597: PolarFire FPGA PCIe Endpoint DDR3L and DDR4 Memory Controller Data Plane Application Note.
  • Download and install Libero SoC on the host PC from the following location: Libero SoC Documentation .

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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