1.5 Reset Structure

The CoreReset_PF synchronizes the external USER_RESETN (SW6 on PolarFire Evaluation kit and SW2 on PolarFire Splash kit) to the DDR4 system clock (200 MHz) and generates the FABRIC_RESET_N, which drives the fabric AXI interface logic. CoreReset_PF uses the DEVICE_INIT_DONE signal, which is asserted when the device initialization is complete. For more information about device initialization, see PolarFire Family Power-Up and Resets User Guide .

For more information on CoreReset_PF IP core, see CoreReset_PF handbook from the Libero catalog.

The DDR3L/DDR4 subsystem does not require a synchronization reset as it has the reset synchronization logic. The following figure shows the reset structure in the reference design.

Figure 1-11. Reset Structure