2.66 Memory Protection Unit (mpu)

Using The Library

Configure the peripheral library using the MCC.

The Memory Protection Unit (MPU) divides the memory map into 8 or 16 regions, and defines the start address, size, memory attributes, data access permission, and instruction access permission.

Memory Attributes: Memory attributes can used to define the memory type and cache behavior.

Strongly Ordered: The processor preserves the transaction order, and the write buffers are not permitted.

Device Memory: The processor preserves the transaction order, and the write buffers are permitted for device access. Device memory is used for memory mapped peripheral registers.

Normal Memory: The processor can re-order transactions for efficiency, or perform speculative reads.

• Write through cache: On hits it writes to the cache and the main memory. On misses it updates the block in the main memory by not bringing that block to the cache.

• Write-back cache: On hits it writes to the cache setting the dirty bit for the block, and the main memory is not updated. On misses it updates the block in the main memory not bringing that block to the cache.

• Write-back with write allocate: On hits it writes to the cache setting dirty bit for the block, the main memory is not updated. On misses it updates the block in the main memory and brings the block to the cache.

• Non-cacheable memory

Data Access Permission:

Data access permission can be used to define FLASH as read-only to protect it from accidental writes and define the non-accessible region to detect stack overflow conditions.

Instruction Access Permission:

Instruction access permission can be used to define non-executable memory region.

Library Interface

Memory Protection Unit peripheral library provides the following interfaces:

Functions