2.15 Cortex-M Cache Controller (CMCC)

The Cortex-M Cache Controller (CMCC) is a 4-Way set associative unified cache controller. It integrates a controller, a tag directory, data memory, metadata memory and a configuration interface.

Using The Library

At runtime, I/D Cache can be enabled or disabled using the corresponding APIs (CMCC_Enable(I/D)Cache and CMCC_Disable(I/D)Cache). When the content of the cache becomes stale, it can be invalidated using the CMCC_InvalidateAll function.

Library Interface

Cortex-M Cache Controller peripheral library provides the following interfaces:

Functions

NameDescription
CMCC_DisableDisable the cortex M cache controller
CMCC_EnableICacheEnables the Instruction cache
CMCC_DisableICacheDisables the Instruction cache
CMCC_EnableDCacheEnables the Data cache
CMCC_DisableDCacheDisables the Data cache
CMCC_InvalidateAllInvalidates the complete cache
Note: Not all APIs maybe implemented. See the specific device family section for available APIs.