30.8 Dual Watchdog Timer (WDT)

Note: This data sheet summarizes the features of the dsPIC33CK1024MP710 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Dual Watchdog Timer” (www.microchip.com/DS70005250).

The dsPIC33 Dual Watchdog Timer (WDT) is described in this section. Refer to Figure 30-2 for a block diagram of the WDT.

The WDT, when enabled, operates from the internal Low-Power RC Oscillator clock source or a selectable clock source in Run mode. The WDT can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. The WDT can be configured in Windowed mode or Non-Windowed mode. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode (Power Save mode). If the WDT expires and issues a device Reset, the WDTO bit in the RCON register will be set.

While the device is reading/writing and executing code from the same Flash Partition, the WDT is intended to stall during this operation and resume its counter after reading/writing from the Flash Partition is complete.

The following are some of the key features of the WDT modules:

  • Configuration or Software Controlled
  • Separate User-Configurable Time-out Periods for Run and Sleep or Idle mode
  • Can Wake the Device from Sleep or Idle mode
  • User-Selectable Clock Source in Run mode
  • Operates from LPRC in Sleep or Idle mode
Note: In Run mode, the WDT counter will pause during NVM operations and resume after NVM programming.
Figure 30-2. Watchdog Timer Block Diagram