8.2.11 GMAC Interrupt Enable Register
This register is write-only and when read will return zero.
The following values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
| Name: | GMAC_IER |
| Offset: | 0x028 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TXLCK | RXLCK | TSUTIMCOMP | WOL | RXLPISBC | SRI | PDRSFT | PDRQFT | ||
| Access | R | R | R | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PDRSFR | PDRQFR | SFT | DRQFT | SFR | DRQFR | ||||
| Access | W | W | W | W | W | W | |||
| Reset | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EXINT | PFTR | PTZ | PFNZ | HRESP | ROVR | ||||
| Access | W | W | W | W | W | W | |||
| Reset | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCOMP | TFC | RLEX | TUR | TXUBR | RXUBR | RCOMP | MFS | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bit 31 – TXLCK Transmit Path Lockup Detected
Bit 30 – RXLCK Receive Path Lockup Detected
Bit 29 – TSUTIMCOMP TSU Timer Comparison (cleared on read)
Indicates when the TSU timer count value is equal to programmed value.