8.2.166 GMAC Express MAC Network Configuration Register

Name: GMAC_EMAC_NCFGR
Offset: 0x1004
Reset: 0x00080000
Property: Read/Write

Bit 3130292827262524 
  IRXERRXBPIPGSEN IRXFCSEFRHDRXCOEN 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
 DCPFDBW[1:0]CLK[2:0]RFCSLFERD 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00001000 
Bit 15141312111098 
 RXBUFO[1:0]PENRTY GBE MAXFS 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
 UNIHENMTIHENNBCCAFJFRAMEDNVLANFDSPD 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 30 – IRXER Ignore Receive Error from PHY

ValueDescription
0

1

GRXER has no effect on the GMAC's operation when GRXDV is low. Set this bit when using the RGMII wrapper in Half Duplex mode.

Bit 29 – RXBP Receive Bad Preamble

ValueDescription
0

Rejects frames with non-standard preamble.

1

Accepts frames with non-standard preamble.

Bit 28 – IPGSEN Inter Packet Gap Stretch Enable

ValueDescription
0

The transmit IPG cannot be increased.

1

The transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG Stretch Register.

Bit 26 – IRXFCS Ignore RX FCS

ValueDescription
0

Normal operation, frames with FCS/CRC errors are rejected.

1

Frames with FCS/CRC errors are rejected. FCS error statistics are still collected for frames with bad FCS and FCS status is recorded in frame’s DMA descriptor.

Bit 25 – EFRHD Enable Frames Received in Half Duplex

ValueDescription
0

Disables frames to be received in Half Duplex mode while transmitting.

1

Enables frames to be received in Half Duplex mode while transmitting.

Bit 24 – RXCOEN Receive Checksum Offload Enable

ValueDescription
0

Disables the receive checksum engine. Frames with bad IP, TCP or UDP checksums are accepted.

1

Enables the receive checksum engine. Frames with bad IP, TCP or UDP checksums are discarded.

Bit 23 – DCPF Disable Copy of Pause Frames

ValueDescription
0

Copies pause frames to the system memory.

1

Prevents valid pause frames being copied to memory. Pause frames are not copied to memory regardless of the state of the Copy All Frames bit, whether a hash match is found or whether a type ID match is identified. If a destination address match is found, the pause frame will be copied to memory. Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required.

Bits 22:21 – DBW[1:0] Always Written to 0

Must be always be written to ‘0’.

Bits 20:18 – CLK[2:0] MDC Clock Division

Set according to MCK speed. These three bits determine the number MCK will be divided by to generate Management Data Clock (MDC). For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations).

ValueNameDescription
0 MCK_8

MCK divided by 8 (MCK up to 20 MHz)

1 MCK_16

MCK divided by 16 (MCK up to 40 MHz)

2 MCK_32

MCK divided by 32 (MCK up to 80 MHz)

3 MCK_48

MCK divided by 48 (MCK up to 120 MHz)

4 MCK_64

MCK divided by 64 (MCK up to 160 MHz)

5 MCK_96

MCK divided by 96 (MCK up to 240 MHz)

Bit 17 – RFCS Remove FCS

ValueDescription
0

Includes the received frame check sequence (last 4 bytes) when writing to memory.

1

Excludes the received frame check sequence (last 4 bytes) when writing to memory. The frame length indicated will be reduced by four bytes in this mode.

Bit 16 – LFERD Length Field Error Frame Discard

ValueDescription
0

Accepts frames with a measured length shorter than the extracted length field

1

Discards frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame). This only applies to frames with a length field less than 0x0600.

Bits 15:14 – RXBUFO[1:0] Receive Buffer Offset

Indicates the number of bytes by which the received data is offset from the start of the receive buffer

Bit 13 – PEN Pause Enable

ValueDescription
0

Does not pause the transmission when a non-zero 802.3 classic pause frame is received.

1

Pauses transmission when a non-zero 802.3 classic pause frame is received and PFC has not been negotiated.

Bit 12 – RTY Retry Test0

ValueDescription
0

Normal operation.

1

The backoff between collisions will always be one slot time and helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every GRXCK cycle.

Bit 10 – GBE Gigabit Mode Enable

ValueDescription
0

Operates in 10/100 Mbps mode.

1

Operates in Gigabit mode.

Bit 8 – MAXFS 1536 Maximum Frame Size

ValueDescription
0

Rejects frame sizes above 1518 bytes.

1

Accepts frames up to 1536 bytes in length. Normally the GMAC would reject any frame above 1518 bytes.

Bit 7 – UNIHEN Unicast Hash Enable

ValueDescription
0

Rejects unicast frames.

1

Accepts unicast frames when the 6-bit hash function of the destination address points to a bit that is set in the Hash register.

Bit 6 – MTIHEN Multicast Hash Enable

ValueDescription
0

Rejects multicast frames.

1

Accepts multicast frames when the 6-bit hash function of the destination address points to a bit that is set in the Hash register.

Bit 5 – NBC No Broadcast

ValueDescription
0

Accepts broadcast frames.

1

Rejects frames addressed to the broadcast address of all ones.

Bit 4 – CAF Copy All Frames

ValueDescription
0

Discards invalid frames.

1

Accepts all valid frames.

Bit 3 – JFRAME Jumbo Frame Size

ValueDescription
0

Disables jumbo frames.

1

Enables jumbo frames up to 16383 bytes to be accepted. The default length is 10240 bytes.

Bit 2 – DNVLAN Discard Non-VLAN FRAMES

ValueDescription
0

Passes all frames to address matching logic

1

Passes only VLAN tagged frames to the address matching logic.

Bit 1 – FD Full Duplex

ValueDescription
0

Half-duplex mode.

1

The transmit block ignores the state of collision and carrier sense and allows receive while transmitting.

Bit 0 – SPD Speed

ValueDescription
0

MAC operates at 10 Mbps.

1

MAC operates at 100 Mbps.