8.2.5 GMAC DMA Configuration Register


Bit	31	30	29	28	27	26	25	24
			TXBD_EXTENDED	RXBD_EXTENDED		TXFOMAXB	RXFOMAXB	DDRP
Access			R/W	R/W		R/W	R/W	R/W
Reset			0	0		0	0	0


Bit	23	22	21	20	19	18	17	16
	DRBS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			CRCERRREP	INFLASTEN	TXCOEN	TXPBMS	RXBMS[1:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ESPA	ESMA		FBLDO[4:0]
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Reset	0	0		0	0	0	0	0

Bit 29 – TXBD_EXTENDED Transmit Buffer Descriptor Extended Mode

See GMAC Transmit Buffer Data Control Register for a description of the features.

Value	Description
0	Disables Transmit Buffer Data Extended mode.
1	Enables Transmit Buffer Data Extended mode.

Bit 28 – RXBD_EXTENDED Receive Buffer Descriptor Extended Mode

See GMAC Receive Buffer Data Control Register for a description of the features.

Value	Description
0	Disables Receive Buffer Data Extended mode.
1	Enables Receive Buffer Data Extended mode.

Bit 26 – TXFOMAXB Force Transmit Max Burst Length

Forces the transmit DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers as defined in FBLDO, even when there is less than max burst data bytes to read. Residual data read is ignored. Does not apply to bursts that break 1k boundary rule.

Bit 25 – RXFOMAXB Force Receive Max Burst Length

Forces the receive DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers, even if there is less than max burst real packet data required to write. Any extra bytes of pad data is set to 0x00. Does not apply to bursts that break 1k boundary rule.

Bit 24 – DDRP DMA Discard Receive Packets

When set, the GMAC DMA automatically discards receive packets from the receiver packet buffer memory when no system memory resource is available.

When low, the received packets remain to be stored in the GMAC local memory packet buffer until a system memory buffer resource becomes available.

A write to this bit is ignored if the DMA is not configured in the packet buffer full store and forward mode.

Bits 23:16 – DRBS[7:0] DMA Receive Buffer Size

DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data.

The value is defined in multiples of 64 bytes, thus a value of 0x01 corresponds to buffers of 64 bytes, 0x02 corresponds to 128 bytes etc.

For example:

– 0x02: 128 bytes

– 0x18: 1536 bytes (1 × max length frame/buffer)

– 0xA0: 10240 bytes (1 × 10K jumbo frame/buffer)

Note that this value should never be written as zero.

Bit 13 – CRCERRREP CRC Errors Report

Value	Description
0	Bit 16 of the receive buffer descriptor represents the Canonical format indicator (CFI) bit as extracted from the receive frame (if the receive buffer descriptor is pointing to the last data buffer of the receive frame and the received frame was VLAN tagged).
1	Bit 16 of the receive buffer descriptor represents the FCS/CRC error (only if frames with FCS are copied to memory as enabled by bit 26 in the Network Configuration register).

Bit 12 – INFLASTEN Infinite Size for Last Buffer Enable

Set to one, this forces the receive DMA to consider the data buffer pointed to by the last descriptor in the descriptor list to be of definite size.

Bit 11 – TXCOEN Transmitter Checksum Generation Offload Enable

Transmitter IP, TCP and UDP checksum generation offload enable. When set, the transmitter checksum generation engine is enabled to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected.

Bit 10 – TXPBMS Transmitter Packet Buffer Memory Size Select

Having this bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GMAC. It is important to set this bit to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 Kbytes.

Value	Name	Description
0	TWO_KB	Do not use top address bit (2 Kbytes).
1	FOUR_KB	Use full configured addressable space (4 Kbytes).

Bits 9:8 – RXBMS[1:0] Receiver Packet Buffer Memory Size Select

The default receive packet buffer size is 8 Kbytes. The table below shows how to configure this memory to FULL, HALF, QUARTER or EIGHTH of the default size.

Value	Name	Description
0	EIGHTH	8/8 Kbyte memory size
1	QUARTER	8/4 Kbytes memory size
2	HALF	8/2 Kbytes memory size
3	FULL	8 Kbytes memory size

Bit 7 – ESPA Endian Swap Mode Enable for Packet Data Accesses

When set, selects swapped endianism for system bus transfers. When clear, selects Little Endian mode.

Value	Name	Description
0	LITTLE_ENDIAN	Selects Little-endian endianism for system bus transfers.
1	BIG_ENDIAN	Selects swapped endianism for system bus transfers.

Bit 6 – ESMA Endian Swap Mode Enable for Management Descriptor Accesses

When set, selects swapped endianism for system bus transfers. When clear, selects Little Endian mode.

Value	Name	Description
0	LITTLE_ENDIAN	Selects Little-endian endianism for system bus transfers.
1	BIG_ENDIAN	Selects swapped endianism for system bus transfers.

Bits 4:0 – FBLDO[4:0] Fixed Burst Length for DMA Data Operations

Selects the burst length to attempt to use on the system bus when transferring frame data. Not used for DMA management operations and only used where space and data size allow. Otherwise system bus single type accesses are used.

Value	Name	Description
0	–	Reserved
1	SINGLE	Always use single access on system bus
2	–	Reserved
4	INCR4	Attempt to use 4-beat bursts on system bus (Default)
8	INCR8	Attempt to use 8-beat bursts on system bus bursts
16	INCR16	Attempt to use 16-beat bursts on system bus bursts

Name:	GMAC_DCFGR
Offset:	0x010
Reset:	0x00000000
Property:	Read/Write