8.2.168 GMAC Express MAC DMA Configuration Register

See GMAC_EMAC_TXBDCTRL for a description of the features.

See GMAC_EMAC_RXBDCTRL for a description of the features.

Forces the transmit DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers as defined in FBLDO, even when there is less than max burst data bytes to read. Residual data read is ignored. Does not apply to bursts that break 1k boundary rule.

Forces the receive DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers, even if there is less than max burst real packet data required to write. Any extra bytes of pad data is set to 0x00. Does not apply to bursts that break 1k boundary rule.

When set, the GMAC DMA will automatically discard receive packets from the receiver packet buffer memory when no system memory resource is available.

When low, the received packets will remain to be stored in the GMAC local memory packet buffer until system memory buffer resource next becomes available.

A write to this bit is ignored if the DMA is not configured in the packet buffer Full Store and Forward mode.

DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data.

The value is defined in multiples of 64 bytes, thus a value of 0x01 corresponds to buffers of 64 bytes, 0x02 corresponds to 128 bytes etc.

For example:

0x02: 128 bytes

0x18: 1536 bytes (1 × max length frame/buffer)

0xA0: 10240 bytes (1 × 10K jumbo frame/buffer)

Note that this value should never be written as zero.

Set to ‘1’, this forces the receive DMA to consider the data buffer pointed to by the last descriptor in the descriptor list to be of definite size.

Transmitter IP, TCP and UDP checksum generation offload enable. When set, the transmitter checksum generation engine is enabled to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected.

This bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GMAC. It is important to set this bit to ‘1’ if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 Kbytes.

The default receive packet buffer size is 8 Kbytes. The table below shows how to configure this memory to FULL, HALF, QUARTER or EIGHTH of the default size.

Selects the burst length to attempt to use on the system bus when transferring frame data. Not used for DMA management operations and only used where space and data size allow. Otherwise system bus single type accesses are used.