6.6.3 CSI Main Interrupt Status Register

The following configuration values are valid for all listed bit names of this register:

0: No event occurred in the corresponding register since the last CSI_INT_ST_MAIN read.

1: An event occurred in the corresponding register since the last CSI_INT_ST_MAIN read.

Name: CSI_INT_ST_MAIN
Offset: 0xC
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       STATUS_INT_LINESTATUS_INT_DPHY 
Access RR 
Reset 00 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 STATUS_INT_ECC_CORRECTEDSTATUS_INT_DATA_IDSTATUS_INT_PLD_CRC_FATALSTATUS_INT_CRC_FRAME_FATALSTATUS_INT_SEQ_FRAME_FATALSTATUS_INT_BNDRY_FRAME_FATALSTATUS_INT_PKT_FATALSTATUS_INT_PHY_FATAL 
Access RRRRRRRR 
Reset 00000000 

Bit 17 – STATUS_INT_LINE CSI_INT_ST_LINE Register Event (cleared on read)

Bit 16 – STATUS_INT_DPHY CSI_INT_ST_DPHY Register Event (cleared on read)

Bit 7 – STATUS_INT_ECC_CORRECTED STATUS_INT_ECC_CORRECTED Register Event (cleared on read)

Bit 6 – STATUS_INT_DATA_ID STATUS_INT_DATA_ID Register Event (cleared on read)

Bit 5 – STATUS_INT_PLD_CRC_FATAL STATUS_INT_PLD_CRC_FATAL Register Event (cleared on read)

Bit 4 – STATUS_INT_CRC_FRAME_FATAL STATUS_INT_CRC_FRAME_FATAL Register Event (cleared on read)

Bit 3 – STATUS_INT_SEQ_FRAME_FATAL STATUS_INT_SEQ_FRAME_FATAL Register Event (cleared on read)

Bit 2 – STATUS_INT_BNDRY_FRAME_FATAL CSI_INT_ST_BNDRY_FRAME_FATAL Register Event (cleared on read)

Bit 1 – STATUS_INT_PKT_FATAL CSI_INT_ST_PKT_FATAL Register Event (cleared on read)

Bit 0 – STATUS_INT_PHY_FATAL CSI_INT_ST_PHY_FATAL Register Event (cleared on read)