6.6.38 CSI Payload CRC Fatal Error Interrupt Mask Register

Name: CSI_INT_MSK_PLD_CRC_FATAL
Offset: 0x2B4
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 ERR_CRC_VC15ERR_CRC_VC14ERR_CRC_VC13ERR_CRC_VC12ERR_CRC_VC11ERR_CRC_VC10ERR_CRC_VC9ERR_CRC_VC8 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 ERR_CRC_VC7ERR_CRC_VC6ERR_CRC_VC5ERR_CRC_VC4ERR_CRC_VC3ERR_CRC_VC2ERR_CRC_VC1ERR_CRC_VC0 
Access RRRRRRRR 
Reset 00000000 

Bit 15 – ERR_CRC_VC15 Mask for ERR_CRC_VC15 (cleared on read)

Bit 14 – ERR_CRC_VC14 Mask for ERR_CRC_VC14 (cleared on read)

Bit 13 – ERR_CRC_VC13 Mask for ERR_CRC_VC13 (cleared on read)

Bit 12 – ERR_CRC_VC12 Mask for ERR_CRC_VC12 (cleared on read)

Bit 11 – ERR_CRC_VC11 Mask for ERR_CRC_VC11 (cleared on read)

Bit 10 – ERR_CRC_VC10 Mask for ERR_CRC_VC10 (cleared on read)

Bit 9 – ERR_CRC_VC9 Mask for ERR_CRC_VC9 (cleared on read)

Bit 8 – ERR_CRC_VC8 Mask for ERR_CRC_VC8 (cleared on read)

Bit 7 – ERR_CRC_VC7 Mask for ERR_CRC_VC7 (cleared on read)

Bit 6 – ERR_CRC_VC6 Mask for ERR_CRC_VC6 (cleared on read)

Bit 5 – ERR_CRC_VC5 Mask for ERR_CRC_VC5 (cleared on read)

Bit 4 – ERR_CRC_VC4 Mask for ERR_CRC_VC4 (cleared on read)

Bit 3 – ERR_CRC_VC3 Mask for ERR_CRC_VC3 (cleared on read)

Bit 2 – ERR_CRC_VC2 Mask for ERR_CRC_VC2 (cleared on read)

Bit 1 – ERR_CRC_VC1 Mask for ERR_CRC_VC1 (cleared on read)

Bit 0 – ERR_CRC_VC0 Mask for ERR_CRC_VC0 (cleared on read)