Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
4 System Controller
5 Analog Subsystem
6 Image Subsystem
- 6.1 Overview
- 6.2 LCD Controller (LCDC)
- 6.3 Low Voltage Differential Signaling Controller (LVDSC)
- 6.4 2D Graphics Engine (GFX2D)
- 6.5 Display Serial Interface (DSI)
- 6.6 Camera Serial Interface (CSI)
  - 6.6.1 Description
  - 6.6.2 Embedded Characteristics
  - 6.6.3 I/O Lines Description
  - 6.6.4 Block Diagram
  - 6.6.5 Product Dependencies
  - 6.6.6 Functional Description
  - 6.6 Register Summary
    - 6.6.1 CSI Lane Configuration Register
      CSI Lane Configuration Register
    - 6.6.2 CSI Reset Control Register
      CSI Reset Control Register
    - 6.6.3 CSI Main Interrupt Status Register
      CSI Main Interrupt Status Register
    - 6.6.4 CSI Data Identifier Register 1
      CSI Data Identifier Register 1
    - 6.6.5 CSI Data Identifier Register 2
      CSI Data Identifier Register 2
    - 6.6.6 CSI Data Identifier Virtual Channel Register 1
      CSI Data Identifier Virtual Channel Register 1
    - 6.6.7 CSI Data Identifier Virtual Channel Register 2
      CSI Data Identifier Virtual Channel Register 2
    - 6.6.8 CSI D-PHY Shutdown Register
      CSI D-PHY Shutdown Register
    - 6.6.9 CSI D-PHY Reset Register
      CSI D-PHY Reset Register
    - 6.6.10 CSI D-PHY Receive Status Register
      CSI D-PHY Receive Status Register
    - 6.6.11 CSI D-PHY Stop State Register
      CSI D-PHY Stop State Register
    - 6.6.12 CSI D-PHY Analog Configuration Control Register
      CSI D-PHY Analog Configuration Control Register
    - 6.6.13 CSI D-PHY Analog Configuration Data Register
      CSI D-PHY Analog Configuration Data Register
    - 6.6.14 CSI Virtual Channel Extension Register
      CSI Virtual Channel Extension Register
    - 6.6.15 CSI D-PHY Calibration Status Register
      CSI D-PHY Calibration Status Register
    - 6.6.16 CSI D-PHY Fatal Error Interrupt Status Register
      CSI D-PHY Fatal Error Interrupt Status Register
    - 6.6.17 CSI D-PHY Fatal Error Interrupt Mask Register
      CSI D-PHY Fatal Error Interrupt Mask Register
    - 6.6.18 CSI D-PHY Fatal Error Interrupt Force Register
      CSI D-PHY Fatal Error Interrupt Force Register
    - 6.6.19 CSI Packet Fatal Error Interrupt Status Register
      CSI Packet Fatal Error Interrupt Status Register
    - 6.6.20 CSI Packet Fatal Error Interrupt Mask Register
      CSI Packet Fatal Error Interrupt Mask Register
    - 6.6.21 CSI Fatal Packet Force Interrupt Register
      CSI Fatal Packet Force Interrupt Register
    - 6.6.22 CSI D-PHY Interrupt Status Register
      CSI D-PHY Interrupt Status Register
    - 6.6.23 CSI D-PHY Interrupt Mask Register
      CSI D-PHY Interrupt Mask Register
    - 6.6.24 CSI D-PHY Interrupt Force Register
      CSI D-PHY Interrupt Force Register
    - 6.6.25 CSI Line Interrupt Status Register
      CSI Line Interrupt Status Register
    - 6.6.26 CSI Line Interrupt Mask Register
      CSI Line Interrupt Mask Register
    - 6.6.27 CSI Line Interrupt Force Register
      CSI Line Interrupt Force Register
    - 6.6.28 CSI Boundary Frame Fatal Error Interrupt Status Register
      CSI Boundary Frame Fatal Error Interrupt Status Register
    - 6.6.29 CSI Boundary Frame Fatal Error Interrupt Mask Register
      CSI Boundary Frame Fatal Error Interrupt Mask Register
    - 6.6.30 CSI Boundary Frame Fatal Error Interrupt Force Register
      CSI Boundary Frame Fatal Error Interrupt Force Register
    - 6.6.31 CSI Frame Sequence Fatal Error Interrupt Status Register
      CSI Frame Sequence Fatal Error Interrupt Status Register
    - 6.6.32 CSI Frame Sequence Fatal Error Interrupt Mask Register
      CSI Frame Sequence Fatal Error Interrupt Mask Register
    - 6.6.33 CSI Frame Sequence Fatal Error Interrupt Force Register
      CSI Frame Sequence Fatal Error Interrupt Force Register
    - 6.6.34 CSI Frame CRC Fatal Error Interrupt Status Register
      CSI Frame CRC Fatal Error Interrupt Status Register
    - 6.6.35 CSI Frame CRC Fatal Error Interrupt Mask Register
      CSI Frame CRC Fatal Error Interrupt Mask Register
    - 6.6.36 CSI Frame CRC Fatal Error Interrupt Force Register
      CSI Frame CRC Fatal Error Interrupt Force Register
    - 6.6.37 CSI Payload CRC Fatal Error Interrupt Status Register
      CSI Payload CRC Fatal Error Interrupt Status Register
    - 6.6.38 CSI Payload CRC Fatal Error Interrupt Mask Register
      CSI Payload CRC Fatal Error Interrupt Mask Register
    - 6.6.39 CSI Payload CRC Fatal Error Interrupt Force Register
      CSI Payload CRC Fatal Error Interrupt Force Register
    - 6.6.40 CSI Data ID Error Interrupt Status Register
      CSI Data ID Error Interrupt Status Register
    - 6.6.41 CSI Data ID Error Interrupt Mask Register
      CSI Data ID Error Interrupt Mask Register
    - 6.6.42 CSI Data ID Error Interrupt Force Register
      CSI Data ID Error Interrupt Force Register
    - 6.6.43 CSI ECC Corrected Interrupt Status Register
      CSI ECC Corrected Interrupt Status Register
    - 6.6.44 CSI ECC Corrected Interrupt Mask Register
      CSI ECC Corrected Interrupt Mask Register
    - 6.6.45 CSI ECC Corrected Interrupt Force Register
      CSI ECC Corrected Interrupt Force Register
    - 6.6.46 CSI Descrambler Configuration Register
      CSI Descrambler Configuration Register
    - 6.6.47 CSI Lane 0 Scrambling Seed Register
      CSI Lane 0 Scrambling Seed Register
    - 6.6.48 CSI Lane 1 Scrambling Seed Register
      CSI Lane 1 Scrambling Seed Register
    - 6.6.49 CSI Lane 2 Scrambling Seed Register
      CSI Lane 2 Scrambling Seed Register
    - 6.6.50 CSI Lane 3 Scrambling Seed Register
      CSI Lane 3 Scrambling Seed Register
- 6.7 CSI-2 Demultiplexer Controller (CSI2DC)
- 6.8 Image Sensor Controller (ISC)
7 Audio Subsystem
8 Security and Cryptography Subsystem
9 Connectivity Subsystem
10 USB Subsystem
11 Electrical and Mechanical Characteristics
12 Revision History
Microchip Information

6.6.4 CSI Data Identifier Register 1

Name:	CSI_DATA_IDS_1
Offset:	0x10
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
			DI3_DT[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
			DI2_DT[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			DI1_DT[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
			DI0_DT[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bits 29:24 – DI3_DT[5:0] Data Type for Programmed Data Identifier 3

Bits 21:16 – DI2_DT[5:0] Data Type for Programmed Data Identifier 2

Bits 13:8 – DI1_DT[5:0] Data Type for Programmed Data Identifier 1

Bits 5:0 – DI0_DT[5:0] Data Type for Programmed Data Identifier 0

DS60001813E

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