6.6.39 CSI Payload CRC Fatal Error
Interrupt Force Register
Name:
CSI_INT_FORCE_PLD_CRC_FATAL
Offset:
0x2B8
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
ERR_CRC_VC15
ERR_CRC_VC14
ERR_CRC_VC13
ERR_CRC_VC12
ERR_CRC_VC11
ERR_CRC_VC10
ERR_CRC_VC9
ERR_CRC_VC8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ERR_CRC_VC7
ERR_CRC_VC6
ERR_CRC_VC5
ERR_CRC_VC4
ERR_CRC_VC3
ERR_CRC_VC2
ERR_CRC_VC1
ERR_CRC_VC0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit 15 – ERR_CRC_VC15 Force ERR_CRC_VC15 (cleared on read)
Bit 14 – ERR_CRC_VC14 Force ERR_CRC_VC14 (cleared on read)
Bit 13 – ERR_CRC_VC13 Force ERR_CRC_VC13 (cleared on read)
Bit 12 – ERR_CRC_VC12 Force ERR_CRC_VC12 (cleared on read)
Bit 11 – ERR_CRC_VC11 Force ERR_CRC_VC11 (cleared on read)
Bit 10 – ERR_CRC_VC10 Force ERR_CRC_VC10 (cleared on read)
Bit 9 – ERR_CRC_VC9 Force ERR_CRC_VC9 (cleared on read)
Bit 8 – ERR_CRC_VC8 Force ERR_CRC_VC8 (cleared on read)
Bit 7 – ERR_CRC_VC7 Force ERR_CRC_VC7 (cleared on read)
Bit 6 – ERR_CRC_VC6 Force ERR_CRC_VC6 (cleared on read)
Bit 5 – ERR_CRC_VC5 Force ERR_CRC_VC5 (cleared on read)
Bit 4 – ERR_CRC_VC4 Force ERR_CRC_VC4 (cleared on read)
Bit 3 – ERR_CRC_VC3 Force ERR_CRC_VC3 (cleared on read)
Bit 2 – ERR_CRC_VC2 Force ERR_CRC_VC2 (cleared on read)
Bit 1 – ERR_CRC_VC1 Force ERR_CRC_VC1 (cleared on read)
Bit 0 – ERR_CRC_VC0 Force ERR_CRC_VC0 (cleared
on read)
DS60001813E
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