50.12.50 SDMMC Retuning Control 2 Register
Name: | SDMMC_RTC2R |
Offset: | 0x211 |
Reset: | – |
Property: | Write-only |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RLD | |||||||||
Access | W | ||||||||
Reset | – |
Bit 0 – RLD Retuning Timer Reload
This bit is only efficient if the Retuning timer is enabled (SDMMC_RTC1R.TMREN set to 1). Once the Timer Counter Value (TCVAL) is set to a nonzero value in SDMMC_RTCVR, setting this bit to 1 starts the timer count. The retuning timer count restarts each time this bit is written to 1.
Writing this bit to 0 has no effect.