30.8.8 Status
Important: For SAM
L11 Non-Secure accesses, write
accesses (W*) are allowed only if Non-Secure Write is set in NONSEC register.
| Name: | STATUS |
| Offset: | 0x18 |
| Reset: | 0x00xx (x determined from latest Set DAL or Chip Erase command) |
| Property: | Write-Secure |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DALFUSE[1:0] | READY | LOAD | PRM | ||||||
| Access | R/R/R | R/R/R | R/R/R | R/R/R | R/R/R | ||||
| Reset | x | x | 0 | 0 | 0 | ||||
Bits 4:3 – DALFUSE[1:0] DAL Fuse Value
| Value | Description |
|---|---|
| 0 | DAL = 0 : Access to very limited features. |
| 1 | DAL = 1 (SAM L11 only): Access to all non-secure memory. Can debug non-secure CPU code. |
| 2 | DAL = 2 : Access to all memory. Can debug Secure and non-secure CPU code. |
| 3 | Reserved |
Bit 2 – READY NVM Ready
| Value | Description |
|---|---|
| 0 | The NVM controller is busy programming or erasing. |
| 1 | The NVM controller is ready to accept a new command. |
Bit 1 – LOAD NVM Page Buffer Active Loading
This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load has been performed, this flag is set. It remains set until a page write or a page buffer clear (PBC) command is given.
Bit 0 – PRM Power Reduction Mode
This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly.
PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM and CPRM) or when exiting sleep with SLEEPPRM set accordingly.
| Value | Description |
|---|---|
| 0 | NVM is not in power reduction mode. |
| 1 | NVM is in power reduction mode. |