31.8.3 Interrupt Enable Set
| Name: | INTENSET |
| Offset: | 0x005 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DRP | ERR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – DRP Data Remanence Prevention Complete Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Data Remanence Prevention Complete Interrupt Enable bit, which enables the data remanence prevention complete interrupt.
| Value | Description |
|---|---|
| 0 | Data remanence prevention complete interrupt is disabled. |
| 1 | Data remanence prevention complete interrupt is enabled. |
Bit 0 – ERR TrustRAM Read Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the TrustRAM Read Error Interrupt Enable bit, which enables the TrustRAM read error interrupt.
| Value | Description |
|---|---|
| 0 | TrustRAM read error interrupt is disabled. |
| 1 | TrustRAM read error interrupt is enabled. |