31.8.1 Control A
| Name: | CTRLA |
| Offset: | 0x000 |
| Reset: | 0x00 |
| Property: | PAC Write Protection, Enable-Protected, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SILACC | DRP | TAMPERS | ENABLE | SWRST | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SILACC Silent Access
Enables differential storage of data.
This bit is not Write-Synchronized.
| Value | Description |
|---|---|
| 0 | Silent access is disabled. |
| 1 | Silent access is enabled. |
Bit 6 – DRP Data Remanence Prevention
Enables periodic DRP in TrustRAM.
This bit is not Write-Synchronized.
| Value | Description |
|---|---|
| 0 | Data remanence prevention is disabled. |
| 1 | Data remanence prevention is enabled. |
Bit 4 – TAMPERS Tamper Erase
Auto-erases TrustRAM and DSCC.DSCKEY on tamper event.
This bit is not Write-Synchronized.
| Value | Description |
|---|---|
| 0 | Tamper erase is disabled. |
| 1 | Tamper erase is enabled. |
Bit 1 – ENABLE Enable
This bit is not Enable-Protected.
| Value | Description |
|---|---|
| 0 | The TRAM is disabled. |
| 1 | The TRAM is enabled. |
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the TRAM to their initial state, and the TRAM will be disabled. This bit can also be set via hardware when a tamper occurs while CTRLA.TAMPERS is set.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same writeoperation will be discarded.
This bit is not Enable-Protected.
Note:
- When the CTRLA.SWRST is written, the user must poll the SYNCBUSY.SWRST bit to know when the reset operation is complete.
- During a SWRST, access to registers/bits without SWRST are disallowed until the SYNCBUSY.SWRST is cleared by hardware.
| Value | Description |
|---|---|
| 0 | There is no reset operation ongoing. |
| 1 | The reset operation is ongoing. |