29.8.6 Interrupt Enable Clear

Important: For SAM L11 Non-Secure accesses, read and write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit).
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x0C
Reset: 0x00000000
Property: PAC Write-Protection, Mix-Secure

Bit 3130292827262524 
 NSCHK        
Access RW/RW/RW 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 EXTINT[7:0] 
Access RW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RWRW/RW*/RW 
Reset 00000000 

Bit 31 – NSCHK Non-secure Check Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the NSCHK Interrupt Enable bit.

Bits 7:0 – EXTINT[7:0] External Interrupt Enable

The bit x of EXTINT enables the interrupt associated with the EXTINTx pin.

Writing a '0' to bit x has no effect.

Writing a '1' to bit x will clear the External Interrupt Enable bit x, which disables the external interrupt EXTINTx.

ValueDescription
0 The external interrupt x is disabled.
1 The external interrupt x is enabled.