29.8.2 Non-Maskable Interrupt Control
Important: For SAM
L11 Non-Secure accesses, read and write accesses (RW*) are allowed only
if the NMI interrupt is set as Non-Secure in the NONSEC register (NONSEC.NMI
bit).
| Name: | NMICTRL |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Mix-Secure |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NMIASYNCH | NMIFILTEN | NMISENSE[2:0] | |||||||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 4 – NMIASYNCH Non-Maskable Interrupt Asynchronous Edge Detection Mode
The NMI edge detection can be operated synchronously or asynchronously to the EIC clock.
| Value | Description |
|---|---|
| 0 | The NMI edge detection is synchronously operated. |
| 1 | The NMI edge detection is asynchronously operated. |
Bit 3 – NMIFILTEN Non-Maskable Interrupt Filter Enable
| Value | Description |
|---|---|
| 0 | NMI filter is disabled. |
| 1 | NMI filter is enabled. |
Bits 2:0 – NMISENSE[2:0] Non-Maskable Interrupt Sense Configuration
These bits define on which edge or level the NMI triggers.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No detection |
| 0x1 | RISE | Rising-edge detection |
| 0x2 | FALL | Falling-edge detection |
| 0x3 | BOTH | Both-edge detection |
| 0x4 | HIGH | High-level detection |
| 0x5 | LOW | Low-level detection |
| 0x6 - 0x7 | - | Reserved |