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13.5.8 PMD7
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | SMT2MD | SMT1MD | CLC4MD | CLC3MD | CLC2MD | CLC1MD | DSM1MD | |
| Access | | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 6 – SMT2MD Disable Signal
Measurement Timer2 bit
| Value | Description |
|---|
1 |
SMT2 module disabled |
0 |
SMT2 module enabled |
Bit 5 – SMT1MD Disable Signal
Measurement Timer1 bit
| Value | Description |
|---|
1 |
SMT1 module disabled |
0 |
SMT1 module enabled |
Bits 1, 2, 3, 4 – CLCnMD Disable CLCn bit
| Value | Description |
|---|
1 |
CLCn module
disabled |
0 |
CLCn module
enabled |
Bit 0 – DSM1MD Disable Data Signal Modulator 1 bit
| Value | Description |
|---|
1 |
DSM1 module disabled |
0 |
DSM1 module enabled |
