17.8.5 CLCxSEL1

Generic CLCx Data 2 Select Register

Name:	CLCxSEL1
Address:	0x1E13,0x1E1D,0x1E27,0x1E31

Bits 5:0 – D2S[5:0] CLCx Data 2 Input Selection bits

Table 17-3. CLC Data Input Sources
D2S Value	CLC Input Source	D2S Value	CLC Input Source
`111111` [63]	Reserved	`011111` [31]	DSM1_out
`111110` [62]	Reserved	`011110` [30]	IOC_flag
`111101` [61]	Reserved	`011101` [29]	ZCD_out
`111100` [60]	Reserved	`011100` [28]	C2_out
`111011` [59]	Reserved	`011011` [27]	C1_out
`111010` [58]	Reserved	`011010` [26]	NCO1_out
`111001` [57]	Reserved	`011001` [25]	PWM7_out
`111000` [56]	Reserved	`011000` [24]	PWM6 _out
`110111` [55]	Reserved	`010111` [23]	CCP4_out
`110110` [54]	Reserved	`010110` [22]	CCP3_out
`110101` [53]	Reserved	`010101` [21]	CCP2_out
`110100` [52]	Reserved	`010100` [20]	CCP1_out
`110011` [51]	EUSART2_CK_out	`010011` [19]	SMT1_overflow
`110010` [50]	EUSART2_DT_out	`010010` [18]	TMR6 _out
`110001` [49]	CCP5_out	`010001` [17]	TMR5 _overflow
`110000` [48]	SMT2_overflow	`010000` [16]	TMR4_out
`101111` [47]	CWG3B_out	`001111` [15]	TMR3 _overflow
`101110` [46]	CWG3A_out	`001110` [14]	TMR2_out
`101101` [45]	CWG2B_out test	`001101` [13]	TMR1_overflow
`101100` [44]	CWG2A_out	`001100` [12]	TMR0_overflow
`101011` [43]	CWG1B_out	`001011` [11]	CLKR_out
`101010` [42]	CWG1A_out	`001010` [10]	FRC
`101001` [41]	MSSP2_clk_out	`001001` [9]	SOSC
`101000` [40]	MSSP2_data_out	`001000` [8]	MFINTOSC (32 kHz)
`100111` [39]	MSSP1_clk_out	`000111` [7]	MFINTOSC (500 kHz)
`100110` [38]	MSSP1_data_out	`000110` [6]	LFINTOSC
`100101` [37]	EUSART1_CK_out	`000101` [5]	HFINTOSC (32 MHz)
`100100` [36]	EUSART1_DT_out	`000100` [4]	F_OSC
`100011` [35]	CLC4_out	`000011` [3]	CLCIN3PPS
`100010` [34]	CLC3_out	`000010` [2]	CLCIN2PPS
`100001` [33]	CLC2_out	`000001` [1]	CLCIN1PPS
`100000` [32]	CLC1_out	`000000` [0]	CLCIN0PPS

Reset States:

POR/BOR = xxxxxx

All Other Resets = uuuuuu