35.4 ZCD Interrupts

An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose.

The ZCDIF bit of the PIR2 register will be set when either edge detector is triggered and its associated enable bit is set. The INTP bit in the ZCDxCON register enables rising edge interrupts and the INTN bit in the ZCDxCON register enables falling edge interrupts.

To fully enable the interrupt, the following bits must be set:

• ZCDIE bit of the PIE2 register
• INTP bit for rising edge detection
• INTN bit for falling edge detection
• PEIE and GIE bits of the INTCON register

Changing the POL bit will cause an interrupt, regardless of the level of the SEN bit.

The ZCDIF bit of the PIR2 register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence.