7.7.4 PIR2
Peripheral Interrupt Request (Flag) Register 2
Note: Interrupt flag bits are
set when an interrupt condition occurs, regardless of the state of
its corresponding enable bit or the Global Enable bit, GIE, of the
INTCON appropriate interrupt flag bits are clear prior to enabling
an interrupt.
| Name: | PIR2 |
| Address: | 0x70E |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ZCDIF | C2IF | C1IF | |||||||
| Access | R/W/HS | R/W/HS | R/W/HS | ||||||
| Reset | 0 | 0 | 0 |
Bit 6 – ZCDIF Zero-Cross Detect Interrupt Flag bit
| Value | Description |
|---|---|
1 |
An enabled rising and/or falling ZCD1 event has been detected (must be cleared in software) |
0 |
No ZCD1 event has occurred |
Bits 0, 1 – CnIF Comparator ‘n’ Interrupt Flag bit
| Value | Description |
|---|---|
1 |
Comparator Cn interrupt asserted (must be cleared in software) |
0 |
Comparator Cn interrupt not asserted |