3.1.2 Metrology Feature Control Register


Bit	31	30	29	28	27	26	25	24
		IN_HARM_DIS	VC_HARM_DIS	IC_HARM_DIS	VB_HARM_DIS	IB_HARM_DIS	VA_HARM_DIS	IA_HARM_DIS
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CREEP_S_EN	CREEP_P_EN	CREEP_Q_EN	CREEP_I_EN		V_MAX_RESET	I_MAX_RESET	SWAP_B_and_C
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0


Bit	15	14	13	12	11	10	9	8
				MAX_INT_SELECT	NEUTRAL_DIS	PHASE_C_EN	PHASE_B_EN	PHASE_A_EN
Access				R/W	R/W	RW	RW	RW
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RZC_THRESH_DIS		SYNCH[1:0]		RZC_DIR	RZC_CHAN_SELECT[2:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		0	0	0	0	0	0

Bit 30 – IN_HARM_DIS

Value	Description
0	Harmonic computation for channel IN (neutral current) is enabled.
1	Harmonic computation for channel IN (neutral current) is disabled.

Bit 29 – VC_HARM_DIS

Value	Description
0	Harmonic computation for channel VC (phase C voltage) is enabled.
1	Harmonic computation for channel VC (phase C voltage) is disabled.

Bit 28 – IC_HARM_DIS

Value	Description
0	Harmonic computation for channel IC (phase C current) is enabled.
1	Harmonic computation for channel IC (phase C current) is disabled.

Bit 27 – VB_HARM_DIS

Value	Description
0	Harmonic computation for channel VB (phase B voltage) is enabled.
1	Harmonic computation for channel VB (phase B voltage) is disabled.

Bit 26 – IB_HARM_DIS

Value	Description
0	Harmonic computation for channel IB (phase B current) is enabled.
1	Harmonic computation for channel IB (phase B current) is disabled.

Bit 25 – VA_HARM_DIS

Value	Description
0	Harmonic computation for channel VA (phase A voltage) is enabled.
1	Harmonic computation for channel VA (phase A voltage) is disabled.

Bit 24 – IA_HARM_DIS

Value	Description
0	Harmonic computation for channel IA (phase A current) is enabled.
1	Harmonic computation for channel IA (phase A current) is disabled.

Bit 23 – CREEP_S_EN Apparent Power Creep Threshold Feature Enable

Used to enable/disable metrology creep function of apparent power pulse generation and any associated ACC_Tx total energy pulse value accumulators. Refer to CREEP_THRESHOLD_S for more information.

Value	Name	Description
0	DISABLED	Disable apparent power creep threshold feature.
1	ENABLED	Enable apparent power creep threshold feature.

Bit 22 – CREEP_P_EN Active Power Creep Threshold Feature Enable

Used to enable/disable metrology creep function of active power pulse generation and any associated ACC_Tx total energy pulse value accumulators. Refer to CREEP_THRESHOLD_P for more information.

Value	Name	Description
0	DISABLED	Disable active power creep threshold feature.
1	ENABLED	Enable active power creep threshold feature.

Bit 21 – CREEP_Q_EN Reactive Power Creep Threshold Feature Enable

Used to enable/disable metrology creep function of reactive power pulse generation and any associated ACC_Tx total quadergy pulse value accumulators. Refer to CREEP_THRESHOLD_Q for more information.

Value	Name	Description
0	DISABLED	Disable reactive power creep threshold feature.
1	ENABLED	Enable reactive power creep threshold feature.

Bit 20 – CREEP_I_EN Current Creep Threshold Feature Enable

Used to enable/disable creep function of metrology, both for pulse generation and any associated ACC_Tx total pulse value accumulators. Current creep thresholding is used to kill pulse contribution from any or all phases below the current threshold and affects all enabled [P, Q, and I²] pulsing. Refer to CREEP_THRESHOLD_I for more information.

Value	Name	Description
0	DISABLED	Disable current creep threshold feature.
1	ENABLED	Enable current creep threshold feature.

Bit 18 – V_MAX_RESET Reset All V_x_MAX values in Metrology Status Registers

This bit will be cleared by the metrology firmware automatically.

Value	Description
1	Reset all V_x_MAX values in Metrology Status Registers.

Bit 17 – I_MAX_RESET Reset All I_x_MAX values in Metrology Status Registers

This bit will be cleared by the metrology firmware automatically.

Value	Description
1	Reset all I_x_MAX values in Metrology Status Registers.

Bit 16 – SWAP_B_and_C Swap I2/V2 to DSP processing channels I_V/V_C and vice versa.

Applies for polyphase processing. Allows Δ-Y transformation when using 2-element ATSense203 metering.

If enabled, channel swap is performed before DSP channel calibration factors are applied.

Value	Description
0	DSP input mapping: I2/V2 mapped I_B/V_B; I3/V3 mapped I_C/V_C (default).
1	DSP input mapping: I2/V2 mapped I_C/V_C; I3/V3 mapped I_B/V_B.

Bit 12 – MAX_INT_SELECT Max Integration Period Select.

Only applies if control word M = 0 (M = Number of cycles for integration period) and affects rounding when determining number of cycles closest to 1 sec.

Value	Description
0	Metrology DSP will integrate for an integral number of cycles closest to 1 second. Due to line frequency drift, the integration period may be slightly longer or shorter than 1 sec, bounded approximately by [0.99, 1.01] sec.
1	Metrology DSP will integrate for an integral number of cycles no greater than 1 second. Due to line frequency drift, the integration period will always be ≤ 1 sec, bounded by approximately by [0.98, 1.00] sec.

Bit 11 – NEUTRAL_DIS Disable neutral measurement.

Only applies when the neutral current and the temperature measurements are shared in the same channel, like in the PIC32CXMTC with external ATSense301. It does not apply to PIC32CXMTSH, including an internal ATSense203.

Value	Description
0	Neutral measurement is disabled, and the shared channel is continuously acquiring temperature readings.
1	Neutral and temperature measurements are acquired using the shared channel.

Bits 8, 9, 10 – PHASE_x_EN Enable Phase x (x = A, B or C).

Selects phases used for pulse computation. At least one phase must be enabled for pulsing to function. For typical usage, enable all phases used for pulsing. This feature may be used to temporarily disable or exclude phases from pulse computation.

Value	Name	Description
0	DISABLED	Disable phase
1	ENABLED	Enable phase

Bit 7 – RZC_THRESH_DIS Raw Zero-Crossing Threshold Disable.

Selects the raw Zero-Crossing detection algorithm threshold.

Value	Description
0	Threshold set to the average value computed in the last integration period.
1	Threshold set to 0.

Bits 5:4 – SYNCH[1:0] Dominant Voltage Channel Selection

The energy integration period is determined by counting zero-crossings of a narrow-band filtered version of the dominant voltage phase. SYNCH is used to allow the metrology module to dynamically determine which voltage phase is the dominant voltage phase or to statically choose one particular phase for zero-crossing counting. In all cases of active phase cycle counting, measurement quantities are integrated over M-number of (negative-to-positive) zero-crossings. We recommend the sync phase is appointed, especially for a single phase application.

Value	Description
0x0	Measurement interval based on dominant phase, determined dynamically.
0x1	Measurement interval based on phase-A.
0x2	Measurement interval based on phase-B.
0x3	Measurement interval based on phase-C.

Bit 3 – RZC_DIR Raw Zero-Crossing Direction Selection

Raw Zero-Crossing Direction selects either positive-going or negative-going raw zero-crossings trigger the IPC interrupt: IPC_RAW_ZERO_CROSSING.

Value	Name	Description
0	POSITIVE	Positive-going raw zero-crossings selected.
1	NEGATIVE	Negative-going raw zero-crossings selected.

Bits 2:0 – RZC_CHAN_SELECT[2:0] Raw Zero-Crossing Channel Select and Enable

Raw Zero-Crossing allows detection of zero-crossings using the raw 16 kHz input voltage channel samples. Unlike the zero-crossing detection used for timing decisions that use a 4 kHz fundamental-only filtered data stream, the Raw Zero-Crossing detection feature has no frequency-dependent group delay nor any appreciable bulk filter delay.

Value	Description
0x0	Raw Zero-Crossing detection is disabled.
0x1	Raw Zero-Crossing detection based on input voltage channel V1.
0x3	Raw Zero-Crossing detection based on input voltage channel V2.
0x5	Raw Zero-Crossing detection based on input voltage channel V3.

Name:	FEATURE_CTRL
Property:	Read-Write