Introduction
1 Definitions, Acronyms and Abbreviations
2 Overall Description
3 Metrology Interface Definition
- 3.1 Metrology Control Registers
  - 3.1.1 Metrology State Control
    Metrology State Control
  - 3.1.2 Metrology Feature Control Register
    Metrology Feature Control Register
  - 3.1.3 Harmonic Control Register
    Harmonic Control Register
  - 3.1.4 Meter Type Settings Register
    Meter Type Settings Register
  - 3.1.5 Number of Line Cycles for Integration Period
    Number of Line Cycles for Integration Period
  - 3.1.6 Max Number of Samples in an Integration Period
    Max Number of Samples in an Integration Period
  - 3.1.7 Pulse Control Register x (x = 0, 1, 2)
    Pulse Control Register x (x = 0, 1, 2)
  - 3.1.8 Meter Active Power Pulse Constant
    Meter Active Power Pulse Constant
  - 3.1.9 Meter Reactive Power Pulse Constant
    Meter Reactive Power Pulse Constant
  - 3.1.10 Meter Current Pulse Constant
    Meter Current Pulse Constant
  - 3.1.11 Meter Apparent Power Pulse Constant
    Meter Apparent Power Pulse Constant
  - 3.1.12 Creep Threshold for Active Energy
    Creep Threshold for Active Energy
  - 3.1.13 Creep Threshold for Quadergy
    Creep Threshold for Quadergy
  - 3.1.14 Creep Threshold of Phase Current
    Creep Threshold of Phase Current
  - 3.1.15 Creep Threshold for Apparent Energy
    Creep Threshold for Apparent Energy
  - 3.1.16 Power Offset Control Register
    Power Offset Control Register
  - 3.1.17 Active Power Offset Register
    Active Power Offset Register
  - 3.1.18 Reactive Power Offset Register
    Reactive Power Offset Register
  - 3.1.19 Apparent Power Offset Register
    Apparent Power Offset Register
  - 3.1.20 Voltage Swell Threshold
    Voltage Swell Threshold
  - 3.1.21 Voltage Sag Threshold
    Voltage Sag Threshold
  - 3.1.22 Current Conversion Factor
    Current Conversion Factor
  - 3.1.23 Voltage Conversion Factor
    Voltage Conversion Factor
  - 3.1.24 Current Channel Magnitude Calibration Constants
    Current Channel Magnitude Calibration Constants
  - 3.1.25 Voltage Channel Magnitude Calibration Constants
    Voltage Channel Magnitude Calibration Constants
  - 3.1.26 Per-Channel Phase Calibration Constants
    Per-Channel Phase Calibration Constants
  - 3.1.27 Waveform Capture Control Register
    Waveform Capture Control Register
  - 3.1.28 Capture Buffer Size
    Capture Buffer Size
  - 3.1.29 Waveform Capture Destination Buffer Address
    Waveform Capture Destination Buffer Address
  - 3.1.30 ATSENSE ADC Control Register 0
    ATSENSE ADC Control Register 0
  - 3.1.31 ATSENSE ADC Control Register 1
    ATSENSE ADC Control Register 1
  - 3.1.32 ATSENSE ADC Control Register 2
    ATSENSE ADC Control Register 2
  - 3.1.33 Per-Phase Active Power Offset Register
    Per-Phase Active Power Offset Register
  - 3.1.34 Per-Phase Reactive Power Offset Register
    Per-Phase Reactive Power Offset Register
- 3.2 Metrology Status Registers
- 3.3 Accumulated Output Quantities
- 3.4 Harmonic Analysis Output Quantities
- 3.5 Derived Output Quantities
4 Interface between Metrology and Application
5 Annex. Meter Forms
The service type determines what meter form is being implemented and how the Metrology DSP core interprets and processes the ADC values.
6 References
7 Revision History
Microchip Information

3.1.30 ATSENSE ADC Control Register 0

This register is a consolidation of ADC control bits for the ATSense AFE, channels: I0, I1, V1 and I2.

Name:	ATSENSE_CTRL_20_23
Property:	Read-Write


Bit	31	30	29	28	27	26	25	24
			I2_GAIN[1:0]					I2_ON
Access			R/W	R/W				R/W
Reset			0	0				0


Bit	23	22	21	20	19	18	17	16
								V1_ON
Access								R/W
Reset								0


Bit	15	14	13	12	11	10	9	8
			I1_GAIN[1:0]					I1_ON
Access			R/W	R/W				R/W
Reset			0	0				0


Bit	7	6	5	4	3	2	1	0
			I0_GAIN[1:0]				TEMPMEAS	I0_ON
Access			R/W	R/W			R/W	R/W
Reset			0	0			0	0

Bits 29:28 – I2_GAIN[1:0] Channel I2 Gain

See ATSense register SDI2, offset 0x23

Value	Description
0x0	Channel has a gain of 1
0x1	Channel has a gain of 2
0x2	Channel has a gain of 4
0x3	Channel has a gain of 8

Bit 24 – I2_ON Enable Channel I2

See ATSense register SDI2, offset 0x23

Value	Description
0x0	Channel is disabled
0x1	Channel is enabled

Bit 16 – V1_ON Enable Channel V1

See ATSense register SDV1, offset 0x22

Value	Description
0x0	Channel is disabled
0x1	Channel is enabled

Bits 13:12 – I1_GAIN[1:0] Channel I1 Gain

See ATSense register SDI1, offset 0x21

Value	Description
0x0	Channel has gain of 1
0x1	Channel has gain of 2
0x2	Channel has gain of 4
0x3	Channel has gain of 8

Bit 8 – I1_ON Enable Channel I1

See ATSense register SDI1, offset 0x21

Value	Description
0x0	Channel is disabled
0x1	Channel is enabled

Bits 5:4 – I0_GAIN[1:0] Channel I0 Gain

See ATSense register SDI0, offset 0x20

Value	Description
0x0	Channel has a gain of 1
0x1	Channel has a gain of 2
0x2	Channel has a gain of 4
0x3	Channel has a gain of 8

Bit 1 – TEMPMEAS Channel I0/Temperature Multiplex Select Bit

See ATSense register SDI0, offset 0x20.

Note: This bit is automatically controlled by the metrology DSP for proper multiplexing between I0 and internal temperature measurement.

Value	Name	Description
0x0	CURRENT_I0	Measurement of external current I0
0x1	TEMP	Measurement of internal temperature sensor

Bit 0 – I0_ON Enable Channel I0

See ATSense register SDI0, offset 0x20

Value	Description
0x0	Channel is disabled
0x1	Channel is enabled

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