3.1.31 ATSENSE ADC Control Register 1
This register is a consolidation of ADC control bits for the ATSense AFE, channels: V2, BIAS.
| Name: | ATSENSE_CTRL_24_27 |
| Property: | Read-Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ONLDO | ONREF | ONBIAS | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| V3_ON | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| I3_GAIN[1:0] | I3_ON | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| V2_ON | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 26 – ONLDO Enable internal LDO (see ATSense register ANA_CTRL, offset 0x27).
| Value | Description |
|---|---|
| 0x0 | Internal LDO is disabled. |
| 0x1 | Internal LDO is enabled. |
Bit 25 – ONREF Enable internal reference (see ATSense register ANA_CTRL, offset 0x27).
| Value | Description |
|---|---|
| 0x0 | Internal reference is disabled. |
| 0x1 | Internal reference is enabled. |
Bit 24 – ONBIAS Enable bias (see ATSense register ANA_CTRL, offset 0x27).
| Value | Description |
|---|---|
| 0x0 | Bias is disabled. |
| 0x1 | Bias is enabled. |
Bit 16 – V3_ON Enable channel V3 (see ATSense register SDV3, offset 0x26)
| Value | Description |
|---|---|
| 0x0 | Channel is disabled. |
| 0x1 | Channel is enabled. |
Bits 13:12 – I3_GAIN[1:0] Channel I3 gain (see ATSense register SDI3, offset 0x25)
| Value | Description |
|---|---|
| 0x0 | Channel has gain of 1. |
| 0x1 | Channel has gain of 2. |
| 0x2 | Channel has gain of 4. |
| 0x3 | Channel has gain of 8. |
Bit 8 – I3_ON Enable channel I3 (see ATSense register SDI3, offset 0x25)
| Value | Description |
|---|---|
| 0x0 | Channel is disabled. |
| 0x1 | Channel is enabled. |
Bit 0 – V2_ON Enable channel V2 (see ATSense register SDV2, offset 0x24)
| Value | Description |
|---|---|
| 0x0 | Channel is disabled. |
| 0x1 | Channel is enabled. |