3.1.32 ATSENSE ADC Control
Register 2
This register is a consolidation of the ADC control bits for the ATSense AFE:
configure registers.
Name: | ATSENSE_CTRL_28_2B |
Property: | Read-Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | MSB_MODE | | | OSR[1:0] | |
Access | | | | R/W | | | R/W | R/W | |
Reset | | | | 0 | | | 0 | 0 | |
Bit 4 – MSB_MODE Mode Selection (see
ATSense register ATCFG, offset 0x28)
Value | Description |
---|
0x0 |
32-bits
mode |
0x1 |
16-bits
mode |
Bits 1:0 – OSR[1:0] Over Sampling Ratio
(see ATSense register ATCFG, offset 0x28)
Value | Description |
---|
0x0 |
System
OSR = 8 |
0x1 |
System
OSR = 16 |
0x2 |
System
OSR = 32 |
0x3 |
System
OSR = 64 |