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Libero IDE v9.x
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13
Libero IDE
13.21
Bus Interfaces
13.21.10
DirectCore Bus Interfaces
13.21.10.4
DBGInterface
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FlashROM, Analog System Builder, and Flash Memory System Builder
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Analog System Builder, FlashROM and Flash Memory System Builder
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ChipEditor
4
Designer Documentation Catalog
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Libero IDE
6
Design Constraints for Software
7
Innoveda eProduct Designer Interface Guide - UNIX
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Innoveda eProduct Designer Interface Guide – Windows
9
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SmartGen Cores Reference
11
HDL Coding Style
12
Libero IDE Documentation Catalog
13
Libero IDE
13
What's New in Libero IDE v9.1
13.1
Supported Families
13.2
Project Management
13.3
Project Files
13.4
Project Options
13.5
Settings
13.6
Preferences
13.7
Project Manager Interface
13.8
Designing with Designer Block Components
13.9
Creating a Designer Block Component in Libero IDE
13.10
Creating a Designer Block Component in Designer
13.11
Instantiating a Designer Block Component in Designer
13.12
SmartDesign
13.13
Getting Started with SmartDesign
13.14
SmartDesign User Interface
13.15
Canvas View
13.16
Grid
13.17
Instance-Instance View
13.18
Schematic View
13.19
Creating a SmartDesign
13.20
Connecting Instances
13.21
Bus Interfaces
13.21.1
About Bus Interfaces
13.21.2
Using Bus Interfaces in SmartDesign
13.21.3
Adding Bus Interfaces to SmartDesign Components
13.21.4
Adding Bus Interfaces to SmartDesign Instances
13.21.5
Removing Bus Interfaces from Instances
13.21.6
Viewing Bus Interface Properties
13.21.7
Modifying Bus Interface Details
13.21.8
Finding Compatible Bus Interfaces
13.21.9
Microchip Bus Interfaces
13.21.10
DirectCore Bus Interfaces
13.21.10.1
AHB
13.21.10.2
APB
13.21.10.3
SysInterface
13.21.10.4
DBGInterface
13.21.10.5
CPInterface
13.21.11
Exposing Bus Interface Pins
13.21.12
Default Tie-offs with Bus Interfaces
13.21.13
Tying Off (Disabling) Unused Bus Interfaces
13.21.14
Required vs. Optional Bus Interfaces
13.21.15
Promoting Bus Interfaces to Top-level
13.22
Incremental Design
13.23
Reference
13.24
Welcome to Designer
13.25
Device Selection
13.26
Design Constraints
13.27
Families Supported
13.28
Entering Constraints
13.29
Running Layout
13.30
Device Programming
13.31
Generating Programming Files
13.32
TCL Command Reference
13.33
Project Manager Tcl Commands
13.34
Reference
13.35
Dialog Boxes
13.36
Revision History
13
Microchip FPGA Support
13
Microchip Information
14
Antifuse Macro Library Guide for Software
15
MultiView Navigator
16
NetlistViewer (non-MVN)
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18
ProASIC and ProASIC PLUS Macro Library for Software
19
PinEditor (non-MVN)
20
SmartPower
21
SmartTime
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
13.21.10.4 DBGInterface
This is the set of debug ports on the CoreMP7 core.
Rev: A
