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Libero IDE v9.x
Libero IDE v9.x
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  2. 5 Libero IDE
  3. 5.13 SmartDesign
  4. 5.13.9 Generating your Design
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  • 1 FlashROM, Analog System Builder, and Flash Memory System Builder
  • 2 Analog System Builder, FlashROM and Flash Memory System Builder
  • 3 ChipEditor
  • 4 Designer Documentation Catalog
  • 5 Libero IDE
    • 5.1 What's New in Libero IDE v9.1
    • 5.2 Supported Families
    • 5.3 Project Management
    • 5.4 Project Files
    • 5.5 Project Options
    • 5.6 Settings
    • 5.7 Preferences
    • 5.8 Project Manager Interface
    • 5.9 Designing with Designer Block Components
    • 5.10 Creating a Designer Block Component in Libero IDE
    • 5.11 Creating a Designer Block Component in Designer
    • 5.12 Instantiating a Designer Block Component in Designer
    • 5.13 SmartDesign
      • 5.13.1 About SmartDesign
      • 5.13.2 SmartDesign Design Flow
      • 5.13.3 Using Existing Projects with SmartDesign
      • 5.13.4 SmartDesign Frequently Asked Questions
      • 5.13.5 General Questions
      • 5.13.6 Instantiating your SmartDesign
      • 5.13.7 Working with Processor-Based Designs in SmartDesign
      • 5.13.8 Making your Design Look Nice
      • 5.13.9 Generating your Design
      • 5.13.10 General Questions
      • 5.13.11 Instantiating Your SmartDesign
      • 5.13.12 Working in SmartDesign
      • 5.13.13 Working with Processor-Based Designs in SmartDesign
      • 5.13.14 Making your Design Look Nice
      • 5.13.15 Generating your Design
    • 5.14 Getting Started with SmartDesign
    • 5.15 SmartDesign User Interface
    • 5.16 Canvas View
    • 5.17 Grid
    • 5.18 Instance-Instance View
    • 5.19 Schematic View
    • 5.20 Creating a SmartDesign
    • 5.21 Connecting Instances
    • 5.22 Bus Interfaces
    • 5.23 Incremental Design
    • 5.24 Reference
    • 5.25 Welcome to Designer
    • 5.26 Device Selection
    • 5.27 Design Constraints
    • 5.28 Families Supported
    • 5.29 Entering Constraints
    • 5.30 Running Layout
    • 5.31 Device Programming
    • 5.32 Generating Programming Files
    • 5.33 TCL Command Reference
    • 5.34 Project Manager Tcl Commands
    • 5.35 Reference
    • 5.36 Dialog Boxes
    • 5.37 Revision History
    • 5 Microchip FPGA Support
    • 5 Microchip Information
  • 6 Design Constraints for Software
  • 7 Innoveda eProduct Designer Interface Guide - UNIX
  • 8 Innoveda eProduct Designer Interface Guide – Windows
  • 9 FlashPro for Software
  • 10 SmartGen Cores Reference
  • 11 HDL Coding Style
  • 12 Libero IDE Documentation Catalog
  • 13 Libero IDE
  • 14 Antifuse Macro Library Guide for Software
  • 15 MultiView Navigator
  • 16 NetlistViewer (non-MVN)
  • 17 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
  • 18 ProASIC and ProASIC PLUS Macro Library for Software
  • 19 PinEditor (non-MVN)
  • 20 SmartPower
  • 21 SmartTime
  • 22 Timer
  • 23 VHDL Vital Simulation
  • 24 Verilog Simulation
  • 25 Technical Support
  • 26 About Microchip

5.13.9 Generating your Design

  1. Ok, I’m done connecting my design, how do I ‘finish’ it so that I can proceed to synthesis?
    1. I get a message saying it’s unable to generate my SmartDesign due to errors, what do I do? What is the Design Rules Check?
  2. Is there an easy way for me to tie off multiple pins at once?

Rev: A

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