5.13.6 Instantiating your SmartDesign

  1. Where is the list of cores that I can instantiate into my SmartDesign?
  2. How do I instantiate cores into my SmartDesign?
  3. I have a block that I wrote in VHDL (or Verilog), can I use that in my SmartDesign?

Working in SmartDesign

  1. How do I make connections?
  2. Auto Connect didn’t connect everything for me; how do I make manual connections?
  3. How do I connect a pin to the top level?
  4. Oops, I just made a connection mistake. How do I disconnect two pins?
  5. I need to apply some simple ‘glue’ logic between my cores. How do I do that?
  6. My logic is a bit more complex than inversion and tie offs - what else can I do?
  7. How do I create a new top level port for my design?
  8. How do I rename one of my instances?
  9. How do I rename my top level port?
  1. How do I rename my group pins?
  2. I need to reconfigure one of my Cores, can I just double click the instance?
  3. I want more Canvas space to work with!