5.13.6 Instantiating your SmartDesign
- Where is the list of cores that I can instantiate into my SmartDesign?
- How do I instantiate cores into my SmartDesign?
- I have a block that I wrote in VHDL (or Verilog), can I use that in my SmartDesign?
- How do I make connections?
- Auto Connect didn’t connect everything for me; how do I make manual connections?
- How do I connect a pin to the top level?
- Oops, I just made a connection mistake. How do I disconnect two pins?
- I need to apply some simple ‘glue’ logic between my cores. How do I do that?
- My logic is a bit more complex than inversion and tie offs - what else can I do?
- How do I create a new top level port for my design?
- How do I rename one of my instances?
- How do I rename my top level port?
