10.5.1.2 Flash*Freeze Management Core I/O Description

The following table describes the core input/output signals of the Flash Freeze Management Core.

Table 10-207. Signals
Signal	Direction	Polarity	Description
Flash_Freeze_n	Input	Active Low	Asynchronous input for Flash*Freeze mode
RST_N	Input	Active Low	Asynchronous Reset
CLK	Input	—	Free running clock to FSM; this is the clock you intend to use for state saving
AUX_CLK1 , ..., AUX_CLK16	Input	—	Other clocks connected to design that need to be filtered
Flash_Freeze_Enabled	Output	High or Low	When asserted this port indicates that the device is entering FlashFreeze.Use this port to drive any logic in your design that needs to be driven by the FlashFreeze state.This port should be used to drive the Flash*Freeze (FF) port of the RAM module generated from the Catalog when present in a design.
WAIT_HOUSEKEEPING	Output	Active High	Signal from the FSM to user logic to start housekeeping as clocks are going to be stalled.
DONE_HOUSEKEEPING	Input	Active High	Signal from User Logic that housekeeping is done and it is safe to stop the clock
CLK_GATED	Output	—	Gated version of CLK (ensures state saving)
AUX_CLK_GATED1, ..., AUX_CLK_GATED16	Output	—	Gated versions of the AUX_CLK1, ..., AUX_CLK16