10.5.1.1.1 Type 1 vs. Type 2

FlashFreeze_FSM

The FlashFreeze_FSM runs in the following order:

1. The FSM makes sure that Flash*Freeze pin is asserted and persistent.
2. The FSM signals to user logic to complete critical operations that are still in process with the signal WAIT_HOUSEKEEPING.
3. User logic indicates that critical operations are complete through the signal DONE_HOUSEKEEPING.
4. The FSM stops the clock connected to user logic using the Filter.
5. The FSM takes the device into Flash*Freeze mode by asserting the LSICC input of the ULSICC macro instantiated inside the Flash*Freeze Management core.
6. The device enters Flash*Freeze mode.
7. When the Flash*Freeze pin is de-asserted, the FSM wakes up. If it wakes up in the incorrect state it self-recovers.
8. On wake-up, the FSM de-asserts the LSICC input and releases the clock to user logic. This enables the FSM to protect the user logic from narrow pulses on the clock and allows critical processes to finish.

Filter

Filters the clocks to user logic based on the control signal received from the FSM; uses the CLKINT global buffer.

A minimum of one Filter exists in the core. There are 17 filters available in the core. The FSM is clocked by the primary clock specified by the user.

HouseKeeping

Your design can enter Flash*Freeze mode at any time, even in the middle of critical tasks. Rather than stop the design clock immediately (as a prelude to entering Flash*Freeze), housekeeping enables you to delay it until the tasks are complete.

User logic determines when the user logic clock stops after the Flash*Freeze pin was asserted.

The housekeeping feature is optional. If you do not use it you can configure Flash*Freeze to bypass housekeeping. To do so, disable Enable Houskeeping in the GUI. This loops back the Wait_Housekeeping output with the Done_Houskeeping input.