7.3.4.1 Design Creation/Verification

During design creation/verification, you capture a design in an RTL-level (behavioral) VHDL source file. After capturing the design, you can perform a behavioral simulation of the VHDL file with the Innoveda SpeedWave software to verify that the VHDL code is correct. You then synthesize the code into a structural VHDL netlist. After synthesis, you can perform a structural simulation of the design. Finally, you generate an EDIF netlist for use in Designer and a VHDL structural netlist for structural and timing simulation in SpeedWave.