24.4.5 Timing Simulation

Use the following procedure to perform a timing simulation on a design. Refer to the documentation included with your simulation tool for additional information about performing timing simulation.

Place-and-route your design in Designer. Refer to the Designer User’s Guide for information about placing-and-routing a design using Designer.
Extract timing information for your design from Designer. From the File menu, click Export. Then, click Timing Files. Choose SDF and click Save (or click Back Annotate). The Back Annotate dialog box is displayed. Create a <design_name>.sdf file by specifying SDF as the CAE type. Click OK.
Create or modify a testbench. Make sure your testbench has an “$sdf_annotate” construct in it. The following is an example testbench with such construct:
```
'timescale 1ns/100ps
module test;
//Inputs and outputs declaration
wire ............
reg ..................
//Instantiate the top module of your design in the test module
<top_module> <instance_name> (.....Pin List...);
...........
//stimulus patterns
initial
begin
.....
end
//Invoke SDF routine to back annotate
initial
$sdf_annotate(“<design_name>.sdf”,<instance_name>);
endmodule
```
The “<instance_name>” variable is the top-level instance name.
Refer to “Example Testbench” for information about creating testbenches.
If your design contains a PLL, you must use a 1ps timescale resolution, for example, ‘timescale 1ns/ps.
Create or modify the command file. A command file is only necessary if you are running batch simulation. Refer to “Example Command File” for information about creating command files.
(VCS Only) Create a PLI table. The PLI table is a text file that contains PLI commands for VCS. The following is an example PLI table called “sdf.tab” that uses the module “test” in the testbench example in step 3.
$sdf_annotate call=sdf_annotate_call acc+=tchk,mp,mip,prx:test+
Refer to the VCS documentation for information about creating a PLI table.
Simulate the design. If your design is a Verilog HDL design, make sure that you simulate the structural Verilog HDL netlist that you generated using Designer or the “edn2vlog” program. Invoke the Verilog simulator by typing the following command (for VCS):
vcs <test_bench>.v <design_name>.v -v $ALSDIR/lib/vlog/<act_fam>.v -M - P sdf.tab
If you are using the migrations libraries, type the following command:
vcs <test_bench>.v <design_name>.v -v $ALSDIR/lib/vlog/<act_fam>.v -v $ALSDIR/lib/vlog/<act_fam>_mig.v -M -P sdf.tab
For other simulators:
<verilog_executable> <test_bench>.v <design_name>.v -v $ALSDIR/lib/vlog/<act_fam>.v
If you are using the migrations libraries, type the following command:
<verilog_executable> <test_bench>.v <design_name>.v -v $ALSDIR/lib/vlog/<act_fam>.v -v $ALSDIR/lib/vlog/<act_fam>_mig.v
The “-v” option is a Verilog switch that you can add to your command line during simulation. Refer to “Verilog Switches” for information.

To simulate a design using a command file,

Invoke the Verilog simulator by typing the following command:

<verilog_executable> -f <command_file>

The “-f ” switch is necessary if you are using a command file to simulate a design.