24.4.3 Behavioral Simulation

Use the following procedure to perform a behavioral simulation of a design. Refer to the documentation included with your simulation tool for additional information about performing behavioral simulation.

Create or modify the testbench. Make sure your testbench has a timescale definition added to it. The following is an example timescale definition:
'timescale 1ns/100ps
Refer to “Example Testbench” for information about creating testbenches.
Create or modify the command file. A command file is only necessary if you are running batch simulation. Refer to “Example Command File” for information.
Simulate the design. If your design is a Verilog HDL design, make sure that you simulate your behavioral Verilog HDL source file. Invoke the Verilog simulator by typing the following command:

```
<verilog_executable> <test_bench>.v <design_name>.v -v
$ALSDIR/lib/vlog/<act_fam>/<act_fam>.v
```
If you are using the migration libraries, type the following command:
```
<verilog_executable> <test_bench>.v <design_name>.v -v
$ALSDIR/lib/vlog/<act_fam>.v -v $ALSDIR/lib/vlog/<act_fam>_mig.v
```
The “-v” option is a Verilog switch that you can add to your command line during simulation.

Refer to “Verilog Switches” for information.

To simulate a design using a command file,

invoke the Verilog simulator by typing the following command:

<verilog_executable> -f <command_file>

The “-f ” switch is necessary if you are using a command file to simulate a design.