24.4.1 Example Testbench

You can use a testbench to apply test vectors or patterns to a design during simulation to compare input and output patterns. The file can instantiate the top-level design, using a Verilog-predefined command, such as “$readmemb,” “$monitor,” and “$display.” To use the testbench, it must be in the current project directory. The following is an example testbench:

'timescale 1ns/100ps
module test;
//Inputs and outputs declaration
wire ............
reg ..................
//Instantiate the top module of your design in the test module
<top_module> <instance_name> (.....Pin List...);
...........
//stimulus patterns
initial
begin
.....
end
endmodule