24.4.2 Example Command File

You can use a command file for batch simulation. Your command file should include all command variables and Verilog switches you want to set during simulation. The following is an example command file:

<test_bench>.v
<design_name>.v
<verilog_switch_1> ... <verilog_switch_n>

The <design_name>.v variable is the Verilog top-level design that includes all design sublevels. This variable can represent a behavioral Verilog design for function simulation or gate-level Verilog design for structural or timing simulation.

The <verilog_switch_1> and <verilog_switch_n> variables represent Verilog switches that you can add to your command line during simulation. Refer to “Verilog Switches” for information about available Verilog switches.