23.2.1.1 Create Design

During design creation/verification, a design is captured in an RTL-level (behavioral) VHDL source file. After capturing the design, you can perform a behavioral simulation of the VHDL file to verify that the VHDL code is correct. The code is then synthesized into a gate-level (structural) VHDL netlist. After synthesis, you can perform an optional pre-layout structural simulation of the design. Finally, an EDIF netlist is generated for use in Libero SoC and a VHDL structural post-layout netlist is generated for timing simulation in a VHDL VITAL-compliant simulator.