20.3.13.1 Sample Equations:

The examples below are for general evaluation purposes only. They are not a precise representation of the actual calculations, since each calculation takes into account family-specific information.

• For a net,

where C is the total capacitive loading of the net (extracted from the routing topology), V is the net's voltage swing, and F is the average switching frequency.

For the ProASIC PLUS family, SmartPower extracts the capacitive loading of a net from a Wire Load model.

• For a module, the power is computed using a characterized library (by family and die-size) describing a specific power model for each type of module. For example, the power model of a flip-flop is given by

where FCK is the average clock-input frequency for this flip-flop, FDOUT is its average data-output frequency, and PCK, PDOUT, PDin are three constants estimated by electrical simulation and silicon characterization for this flip-flop module, and FDin is its average data-input frequency.

• For an I/O, the formula used for computing the power consumption depends on the I/O technology and the family. For example, for a TTL output, the dynamic power is given by

  

  where C is the output load (derived from what you have set in the I/O Attribute Editor GUI, typically 35 pF for TTL), V is the output's voltage swing (3.3 V for TTL), and PINT represents an internal power contribution dissipated in the pad, and F is the average switching frequency of the I/O.

• For a complex block, like a RAM, a FIFO, or a PLL, SmartPower uses a high-level power model that integrates design parameters.

SmartPower automatically computes all the constant parameters of these equations. However, the frequencies depend on the target frequencies of your design. Since it is impractical to enter each frequency manually, SmartPower has several flows that help you to estimate the frequencies and calculate the power consumption.