11.4.9.1 Register-Based Single Port SRAM

The following example shows the behavioral model for a 8x8 RAM cell. To modify the width or depth, simply modify the listed parameters in the code. The code assumes that you want to use “posedge clk” and “negedge reset.” Modify the “always” blocks if that is not the case.

VHDL

-- *************************************************
-- Behavioral description of a single-port SRAM with:
-- Active High write enable (WE)
-- Rising clock edge (Clock)
-- *************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity reg_sram is
generic (width : integer:=8;
depth : integer:=8;
addr : integer:=3);
port (Data : in std_logic_vector (width-1 downto 0);
Q : out std_logic_vector (width-1 downto 0);
Clock : in std_logic;
WE : in std_logic;
Address : in std_logic_vector (addr-1 downto 0));
end reg_sram;
architecture behav of reg_sram is
type MEM is array (0 to depth-1) of std_logic_vector(width-1
downto 0);
signal ramTmp : MEM;
begin
process (Clock)
begin
if (clock'event and clock='1') then
if (WE = '1') then
ramTmp (conv_integer (Address)) <= Data;
end if;
end if;
end process;
Q <= ramTmp(conv_integer(Address));
end behav;

Verilog

`timescale 1 ns/100 ps
//########################################################
//# Behavioral single-port SRAM description :
//# Active High write enable (WE)
//# Rising clock edge (Clock)
//#######################################################
module reg_sram (Data, Q, Clock, WE, Address);
parameter width = 8;
parameter depth = 8;
parameter addr = 3;
input Clock, WE;
input [addr-1:0] Address;
input [width-1:0] Data;
output [width-1:0] Q;
wire [width-1:0] Q;
reg [width-1:0] mem_data [depth-1:0];
always @(posedge Clock)
if(WE)
mem_data[Address] = #1 Data;
assign Q = mem_data[Address];
endmodule