11.4.9.2 Register-Based Dual-Port SRAM
The following example shows the behavioral model for a 8x8 RAM cell. This code was designed to imitate the behavior of the Microchip DX family dual-port SRAM and to be synthesizeable to a register based SRAM module. To modify the width or depth, modify the listed parameters in the code. The code assumes that you want to use “posedge clk” and “negedge reset.” Modify the “always” blocks if that is not the case.
VHDL
-- Behavioral description of dual-port SRAM with :
-- Active High write enable (WE)
-- Active High read enable (RE)
-- Rising clock edge (Clock)
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity reg_dpram is
generic (width : integer:=8;
depth : integer:=8;
addr : integer:=3);
port (Data : in std_logic_vector (width-1 downto 0);
Q : out std_logic_vector (width-1 downto 0);
Clock : in std_logic;
WE : in std_logic;
RE : in std_logic;
WAddress: in std_logic_vector (addr-1 downto 0);
RAddress: in std_logic_vector (addr-1 downto 0));
end reg_dpram;
architecture behav of reg_dpram is
type MEM is array (0 to depth-1) of std_logic_vector(width-1
downto 0);
signal ramTmp : MEM;
begin
-- Write Functional Section
process (Clock)
begin
if (clock'event and clock='1') then
if (WE = '1') then
ramTmp (conv_integer (WAddress)) <= Data;
end if;
end if;
end process;
-- Read Functional Section
process (Clock)
begin
if (clock'event and clock='1') then
if (RE = '1') then
Q <= ramTmp(conv_integer (RAddress));
end if;
end if;
end process;
end behav;Verilog
`timescale 1 ns/100 ps
//########################################################
//# Behavioral dual-port SRAM description :
//# Active High write enable (WE)
//# Active High read enable (RE)
//# Rising clock edge (Clock)
//#######################################################
module reg_dpram (Data, Q, Clock, WE, RE, WAddress, RAddress);
parameter width = 8;
parameter depth = 8;
parameter addr = 3;
input Clock, WE, RE;
input [addr-1:0] WAddress, RAddress;
input [width-1:0] Data;
output [width-1:0] Q;
reg [width-1:0] Q;
reg [width-1:0] mem_data [depth-1:0];
// #########################################################
// # Write Functional Section
// #########################################################
always @(posedge Clock)
begin
if(WE)
mem_data[WAddress] = #1 Data;
end
//#########################################################
//# Read Functional Section
//#########################################################
always @(posedge Clock)
begin
if(RE)
Q = #1 mem_data[RAddress];
end
endmodule