8.5.2.1 Design Creation/Verification

During design creation/verification, a schematic representation of a design is captured using the eProduct Designer ViewDraw software. After design capture, you can perform a prelayout (functional) simulation with the ePD ViewSim software. Finally, an EDIF netlist is generated for use in Designer.

Schematic Capture

Enter your schematic in ViewDraw. For information about using ViewDraw, see Microchip-Innoveda Design Considerations and the Innoveda documentation.

Functional Simulation

Perform a functional simulation of your design using ViewSim before generating an EDIF netlist for place-and-route. Functional simulation verifies that the logic of the design is correct. Unit delays are used for all gates during functional simulation. For information about performing functional simulation, see Functional Simulation and the Innoveda documentation.

EDIF Netlist Generation

After you have captured and verified your design, you must generate an EDIF netlist for place-and-route in Designer. For information about generating an EDIF netlist, see Generating an EDIF Netlist.