8.5.4 VHDL Synthesis-Based Design Flow Overview

The Actel-Innoveda VHDL synthesis-based design flow has four main steps; design creation/ verification, design implementation, programming, and system verification. Two verification tools are described, SpeedWave and ViewSim. Use SpeedWave if it is available. It is a VHDL simulator that allows you to perform behavioral, structural, and timing simulation. It also allows you to write stimulus in VHDL. If SpeedWave is not available, use ViewSim for structural and timing simulation. A description of these steps follows.