11.4.5.2 CLKBUF

The following examples instantiate a CLKBUF driver.

Figure 11-40. CLKBUF Driver
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity design is
port (PAD : in std_logic;
Y : out std_logic);
end component;
begin
-- Concurrent Statement
U2 : CLKBUF port map (PAD => reset, Y => rst_rst);
end rtl;
Verilog
module design (……………);
input …………………;
output …………………;
CLKBUF U2 (.Y(rst), .PAD(reset));
……………………
……………………
endmodule